IDT71V546S_08 datasheet(9/21 Pages) IDT

Part #	IDT71V546S

Description	3.3V Synchronous SRAM

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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9 / 21 page

6.42

9

IDT71V546, 128K x 36, 3.3V Synchronous SRAM with

ZBT

™

™ Feature, Burst Counter and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Read Operation(1)

NOTE:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance..

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

Burst Read Operation(1)

NOTE:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

Cycle

Address

R/W

ADV/LD

CE(2)

CEN

BWx

OE

I/O

Comments

n

A0

H

L

X

Address and Control meet setup

n+1

X

L

XXX

Clock Setup Valid

n+2

X

L

Q0

Contents of Address A0 Read Out

3821 tbl 12

Cycle

Address

R/W

ADV/LD

CE(2)

CEN

BWx

OE

I/O

Comments

n

A0

H

L

X

Address and Control meet setup

n+1

X

H

X

L

X

Clock Setup Valid, Advance Counter

n+2

X

H

X

L

X

L

Q0

Address A0 Read Out, Inc. Count

n+3

X

H

XL

Q0+1

Address A0+1 Read Out, Inc. Count

n+4

X

H

XL

Q0+2

Address A0+2 Read Out, Inc. Count

n+5

A1

H

L

X

L

Q0+3

Address A0+3 Read Out, Load A1

n+6

X

H

X

L

X

L

Q0

Address A0 Read Out, Inc. Count

n+7

X

H

X

L

X

L

Q1

Address A1 Read Out, Inc. Count

n+8

A2

H

L

X

L

Q1+1

Address A1+1 Read Out, Load A2

3821 tbl 13

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