6.42

7

IDT71V546, 128K x 36, 3.3V Synchronous SRAM with

ZBT

™

™

™

™

™ Feature, Burst Counter and Pipelined Outputs

Commercial and Industrial Temperature Ranges

NOTE:

2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data

delay from the rising edge of clock.

A37

C37

D/Q35

n+29

A29

C29

D/Q27

ADDRESS

(A0 - A16)

CONTROL

(R

/W, ADV/LD, BWx)

DATA

I/O [0:31], I/O P[1:4]

CYCLE

CLOCK

n+30

A30

C30

D/Q28

n+31

A31

C31

D/Q29

n+32

A32

C32

D/Q30

n+33

A33

C33

D/Q31

n+34

A34

C34

D/Q32

n+35

A35

C35

D/Q33

n+36

A36

C36

D/Q34

(2)

(2)

(2)

3821 drw 03

n+37

A37

C37

D/Q35

,

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1

A0

A1

A0

A1

A0

A1

A0

First Address

0

0

0

1

1

0

1

1

Second Address

0

1

0

0

1

1

1

0

Third Address

1

0

1

1

0

0

0

1

11

1

0

0

1

00

3821 tbl 09

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1

A0

A1

A0

A1

A0

A1

A0

First Address

0

0

0

1

1

0

1

1

Second Address

0

1

1

0

1

1

0

0

Third Address

1

0

1

1

0

0

0

1

11

00

0

1

1

0

3821 tbl 10