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IDT71V546S Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT71V546S Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 21 page 4 IDT71V546, 128K x 36, 3.3V Synchronous SRAM with ZBT ™ ™ ™ ™ ™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges Pin Configuration — 128K X 36 100 99989796 9594 939291 90 87 86858483 8281 89 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O31 I/O30 VDD VSS I/O29 I/O28 I/O27 I/O26 VSS VDD I/O25 I/O24 VSS VDD I/O23 I/O22 VDD VSS I/O21 I/O20 I/O19 I/O18 VSS VDD I/O17 I/O16 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 I/O14 VDD VSS I/O13 I/O12 I/O11 I/O10 VSS VDD I/O9 I/O8 VSS VDD I/O7 I/O6 VDD VSS I/O5 I/O4 I/O3 I/O2 VSS VDD I/O1 I/O0 PK100-1 3821 drw 02 VDD(1) I/O15 I/OP3 VDD I/OP4 I/OP1 VDD I/OP2 VSS . . NOTES: 1. Pin 14 does not have to be connected directly to VDD as long as the input voltage is > VIH. 2. Pins 83 and 84 are reserved for future A17 (8M) and A18 (16M) respectively. 100 100 100 100 100 T TT T TQFP QFP QFP QFP QFP T TT T Top op op op op V V V V Vie ie ie ie iew w w w w |
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