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IDT71T75702 Datasheet(PDF) 15 Page - Integrated Device Technology |
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IDT71T75702 Datasheet(HTML) 15 Page - Integrated Device Technology |
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15 / 26 page  6.42 IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges 15 AC Electrical Characteristics (VDD = 2.5V±5%, Commercial and Industrial Temperature Ranges) NOTES: 1. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ. 2. Transition is measured ±200mV from steady-state. 3. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested. 4. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 2.625V) than tCHZ, which is a Max. parameter (worse case at 70 deg. C, 2.375V). 7.5ns 8ns 8.5ns Symbol Parameter Min. Max. Min. Max. Min. Max. Unit tCYC Clock Cycle Time 10 ____ 10.5 ____ 11 ____ ns tCH (1) Clock High Pulse Width 2.5 ____ 2.7 ____ 3.0 ____ ns tCL (1) Clock Low Pulse Width 2.5 ____ 2.7 ____ 3.0 ____ ns Output Parameters tCD Clock High to Valid Data ____ 7.5 ____ 8 ____ 8.5 ns tCDC Clock High to Data Change 2 ____ 2 ____ 2 ____ ns tCLZ (2,3,4) Clock High to Output Active 3 ____ 3 ____ 3 ____ ns tCHZ(2,3,4) Clock High to Data High-Z ____ 5 ____ 5 ____ 5ns tOE Output Enable Access Time ____ 5 ____ 5 ____ 5ns tOLZ (2,3) Output Enable Low to Data Active 0 ____ 0 ____ 0 ____ ns tOHZ (2,3) Output Enable High to Data High-Z ____ 5 ____ 5 ____ 5ns Set Up Times tSE Clock Enable Setup Time 2.0 ____ 2.0 ____ 2.0 ____ ns tSA Address Setup Time 2.0 ____ 2.0 ____ 2.0 ____ ns tSD Data In Setup Time 2.0 ____ 2.0 ____ 2.0 ____ ns tSW Read/Write (R/ W) Setup Time 2.0 ____ 2.0 ____ 2.0 ____ ns tSADV Advance/Load (ADV/ LD) Setup Time 2.0 ____ 2.0 ____ 2.0 ____ ns tSC Chip Enable/Select Setup Time 2.0 ____ 2.0 ____ 2.0 ____ ns tSB Byte Write Enable ( BWx) Setup Time 2.0 ____ 2.0 ____ 2.0 ____ ns Hold Times tHE Clock Enable Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tHA Address Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tHD Data In Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tHW Read/Write (R/ W) Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tHADV Advance/Load (ADV/ LD) Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tHC Chip Enable/Select Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tHB Byte Write Enable ( BWx) Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns 5319 tbl 24 |
Similar Part No. - IDT71T75702_09 |
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Similar Description - IDT71T75702_09 |
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