6.42

IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

21

JTAG Interface Specification

TCK

TDI/TMS

TDO

M5319 drw 01

x

Symbol

Parameter

Min.

Max.

Units

JTAG Clock Input Period

100

____

ns

JTAG Clock HIGH

40

____

ns

JTAG Clock Low

40

____

ns

JTAG Clock Rise Time

____

5

(1)

ns

JTAG Clock Fall Time

____

5

(1)

ns

JTAG Reset

50

____

ns

JTAG Reset Recovery

50

____

ns

JTAG Data Output

____

20

ns

JTAG Data Output Hold

0

____

ns

JTAG Setup

25

____

ns

JTAG Hold

25

____

ns

I5319 tbl 01

Register Name

Bit Size

Instruction (IR)

4

Bypass (BYR)

1

JTAG Identification (JIDR)

32

Boundary Scan (BSR)

Note (1)

I5319 tbl 03

NOTES:

1. Device inputs = All device inputs except TDI, TMS and

TRST.

2. Device outputs = All device outputs except TDO.

3. During power up,

TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.

NOTE:

1. The Boundary Scan Descriptive Language (BSDL) file for this device is available

by contacting your local IDT sales representative.

JTAG AC Electrical

Scan Register Sizes

NOTES:

1. Guaranteed by design.

2. AC Test Load (Fig. 1) on external output signals.

3. Refer to AC Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.