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IDT7035S Datasheet(PDF) 11 Page - Integrated Device Technology |
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IDT7035S Datasheet(HTML) 11 Page - Integrated Device Technology |
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11 / 19 page  6.42 IDT7035S/L High-Speed 8K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges 11 NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/S = VIH)" or "Timing Waveform of Write with Port-To-Port Delay (M/S = VIH)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual) or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited on Port "B" during contention with Port "A". 5. To ensure that a write cycle is completed on Port "B" after contention with Port "A". 6. 'X' in part numbers indicates power rating (S or L). AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6) Symbol Parameter 7035X15 Com'l Only 7035X20 Com'l & Ind Unit Min. Max. Min. Max. BUSY TIMING (M/S=VIH) tBAA BUSY Access Time from Address Match ____ 15 ____ 20 ns tBDA BUSY Disable Time from Address Not Matched ____ 15 ____ 20 ns tBAC BUSY Access Time from Chip Enable Low ____ 15 ____ 20 ns tBDC BUSY Access Time from Chip Enable High ____ 15 ____ 17 ns tAPS Arbitration Priority Set-up Time(2) 5 ____ 5 ____ ns tBDD BUSY Disable to Valid Data(3) ____ 18 ____ 30 ns tWH Write Hold After BUSY(5) 12 ____ 15 ____ ns BUSY TIMING (M/S=VIL) tWB BUSY Input to Write(4) 0 ____ 0 ____ ns tWH Write Hold After BUSY(5) 12 ____ 15 ____ ns PORT-TO-PORT DELAY TIMING tWDD Write Pulse to Data Delay(1) ____ 30 ____ 45 ns tDDD Write Data Valid to Read Data Delay(1) ____ 25 ____ 30 ns 4088 tbl 14 |
Similar Part No. - IDT7035S_15 |
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Similar Description - IDT7035S_15 |
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