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IDT7035S Datasheet(PDF) 16 Page - Integrated Device Technology |
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IDT7035S Datasheet(HTML) 16 Page - Integrated Device Technology |
16 / 19 page ![]() 6.42 IDT7035S/L High-Speed 8K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges 16 Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7035 RAMs. Busy Logic BusyLogicprovidesahardwareindicationthatbothportsoftheRAM haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe twoaccessestoproceedandsignalstheothersidethattheRAMis“busy”. The BUSYpincanthenbeusedtostalltheaccessuntiltheoperationon theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally to prevent the write from proceeding. TheuseofBUSYlogicisnotrequiredordesirableforallapplications. InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether and use any BUSY indication as an interrupt source to flag the event of anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT7035 RAM in master mode, are push- pull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate. Width Expansion with BUSY Logic Master/Slave Arrays WhenexpandinganIDT7035RAMarrayinwidthwhileusingBUSY logic, one master part is used to decide which side of the RAM array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT7035 RAM the BUSY pinisanoutputifthepartisusedasamaster(M/S= VIH),andthe BUSY pin is an input if the part used as a slave (M/S = VIL) as shown in Figure 3. Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit decisioncouldresultwithonemasterindicatingBUSYononesideofthe arrayandanothermasterindicatingBUSYononeothersideofthearray. Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword. The BUSY arbitration, on a master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite pulsecanbeinitiatedwitheithertheR/Wsignalorthebyteenables.Failure toobservethistimingcanresultinaglitchedinternalwriteinhibitsignaland corrupted data in the slave. Semaphores TheIDT7035isanextremelyfastDual-Port8Kx18CMOSStaticRAM withanadditional8addresslocationsdedicatedtobinarysemaphoreflags. TheseflagsalloweitherprocessorontheleftorrightsideoftheDual-Port RAMtoclaimaprivilegeovertheotherprocessorforfunctionsdefinedby thesystemdesigner’ssoftware.Asanexample,thesemaphorecanbe usedbyoneprocessortoinhibittheotherfromaccessingaportionofthe Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, and both ports are completelyindependentofeachother.Thismeansthattheactivityonthe left port in no way slows the access time of the right port. Both ports are identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom, orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe simultaneous writing of, or a simultaneous READ/WRITE of, a non- semaphorelocation.Semaphoresareprotectedagainstsuchambiguous situationsandmaybeusedbythesystemprogramtoavoidanyconflicts inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol on-chip power down circuitry that permits the respective port to go into standbymodewhennotselected. Thisistheconditionwhichisshownin Truth Table I where CE and SEM = VIH. SystemswhichcanbestusetheIDT7035containmultipleprocessors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT7035's hardware semaphores, which provide a lockout mechanism without requiring complexprogramming. Software handshaking between processors offers the maximum in systemflexibilitybypermittingsharedresourcestobeallocatedinvarying configurations.TheIDT7035doesnotuseitssemaphoreflagstocontrol anyresourcesthroughhardware,thusallowingthesystemdesignertotal flexibilityinsystemarchitecture. An advantage of using semaphores rather than the more common methodsofhardwarearbitrationisthatwaitstatesareneverincurredin either processor. This can prove to be a major advantage in very high- speedsystems. How the Semaphore Flags Work Thesemaphorelogicisasetofeightlatcheswhichareindependent oftheDual-PortRAM.Theselatchescanbeusedtopassaflag,ortoken, fromoneporttotheothertoindicatethatasharedresourceisinuse.The semaphores provide a hardware assist for a use assignment method called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft processorwantstousethisresource,itrequeststhetokenbysettingthe latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading it. If it was successful, it proceeds to assume control over the shared resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe rightsideprocessorhassetthelatchfirst, hasthetokenandisusingthe 4088 drw 17 MASTER Dual Port RAM BUSYL BUSYR CE SLAVE Dual Port RAM BUSYL BUSYR CE BUSYL BUSYR MASTER Dual Port RAM BUSYL BUSYR CE SLAVE Dual Port RAM BUSYL BUSYR CE . |
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