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IDT7005S Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT7005S Datasheet(HTML) 10 Page - Integrated Device Technology |
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10 / 21 page  6.42 IDT7005S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges 10 Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) NOTES: 1. R/W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5) CE or SEM(9) R/ W tWC tHZ (7) tAW tWR (3) tAS (6) tWP (2) DATAOUT tWZ (7) tDW tDH tOW OE ADDRESS DATAIN (4) (4) 2738 drw 09 2738 drw 10 tWC tAS (6) tWR (3) tDW tDH ADDRESS DATAIN CE or SEM(9) R/ W tAW tEW (2) |
Similar Part No. - IDT7005S_16 |
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Similar Description - IDT7005S_16 |
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