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IDT7005S Datasheet(PDF) 17 Page - Integrated Device Technology |
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IDT7005S Datasheet(HTML) 17 Page - Integrated Device Technology |
17 / 21 page 6.42 IDT7005S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges 17 Busy Logic BusyLogicprovidesahardwareindicationthatbothportsoftheRAM haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe twoaccessestoproceedandsignalstheothersidethattheRAMis“busy”. TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally to prevent the write from proceeding. TheuseofBUSYlogicisnotrequiredordesirableforallapplications. InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether and use any BUSY indication as an interrupt source to flag the event of anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. TheBUSYoutputsontheIDT7005RAMinmastermode,arepush- pull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate. Width Expansion with Busy Logic Master/Slave Arrays WhenexpandinganIDT7005RAMarrayinwidthwhileusingBUSY logic, one master part is used to decide which side of the RAM array will receive a BUSY indication, and to output that indication. Any number of slavestobeaddressedinthesameaddressrangeasthemaster,usethe BUSY signalasawriteinhibitsignal.ThusontheIDT7005RAMtheBUSY pinisanoutputifthepartisusedasamaster(M/Spin=VIH),andtheBUSY pin is an input if the part used as a slave (M/S pin = VIL) as shown in Figure 3. Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit decisioncouldresultwithonemasterindicatingBUSYononesideofthe arrayandanothermasterindicatingBUSYononeothersideofthearray. Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword. The BUSY arbitration on a master is based on the chip enable and Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7005 RAMs. address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actualwritepulsecanbeinitiatedwiththeR/Wsignal.Failuretoobserve thistimingcanresultinaglitchedinternalwriteinhibitsignalandcorrupted data in the slave. Semaphores TheIDT7005isanextremelyfastDual-Port8Kx8CMOSStaticRAM withanadditional8addresslocationsdedicatedtobinarysemaphoreflags. TheseflagsalloweitherprocessorontheleftorrightsideoftheDual-Port RAMtoclaimaprivilegeovertheotherprocessorforfunctionsdefinedby thesystemdesigner’ssoftware.Asanexample,thesemaphorecanbe usedbyoneprocessortoinhibittheotherfromaccessingaportionofthe Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, and both ports are completelyindependentofeachother.Thismeansthattheactivityonthe left port in no way slows the access time of the right port. Both ports are identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom, orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe simultaneous writing of, or a simultaneous READ/WRITE of, a non- semaphorelocation.Semaphoresareprotectedagainstsuchambiguous situationsandmaybeusedbythesystemprogramtoavoidanyconflicts inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol on-chip power down circuitry that permits the respective port to go into standbymodewhennotselected. Thisistheconditionwhichisshownin Truth Table I where CE and SEM are both HIGH. SystemswhichcanbestusetheIDT7005containmultipleprocessors or controllers and are typically very high-speed systems which are softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom aperformanceincreaseofferedbytheIDT7005'shardwaresemaphores, whichprovidealockoutmechanismwithoutrequiringcomplexprogram- ming. Software handshaking between processors offers the maximum in systemflexibilitybypermittingsharedresourcestobeallocatedinvarying 2738 drw 19 MASTER Dual Port RAM BUSY (R) CE MASTER Dual Port RAM BUSY (R) CE SLAVE Dual Port RAM BUSY (R) CE SLAVE Dual Port RAM BUSY (R) CE BUSY (L) BUSY (R) BUSY (L) BUSY (L) BUSY (L) BUSY (L) , |
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