ADuCM322i

Data Sheet

Rev. 0 | Page 18 of 23

Pin No.

Mnemonic

Type1

Description

G2

P3.1/PRTADDR1/PLAI[13]

I/O

Digital Input/Output Port 3.1 (P3.1).

MDIO Port Address Bit 1 (PRTADDR1). See the Digital Inputs parameter in

Table 1 for details.

Input to PLA Element 13 (PLAI[13]).

G3

P3.0/PRTADDR0/PLAI[12]

I/O

Digital Input/Output Port 3.0 (P3.0).

MDIO Port Address Bit 0 (PRTADDR0). See the Digital Inputs parameter in

Table 1 for details.

Input to PLA Element 12 (PLAI[12]).

G9

AIN15/P4.7

AI/I/O

Analog Input 15 (AIN15).

Digital Input/Output Port 4.7 (P4.7).

G10

AIN13/P4.5

AI/I/O

Analog Input 13 (AIN13).

Digital Input/Output Port 4.5 (P4.5).

G11

AVDD4

S

ADC Supply (3.3 V).

H1

P3.5/MCK/PLAO[27]

I/O

Digital Input/Output Port 3.5 (P3.5).

MDIO Clock (MCK). See the Digital Inputs parameter in Table 1 for more details.

Output of PLA Element 27 (PLAO[27]).

H2

XTALO

O

Output from the Crystal Oscillator Inverter. When not using an external

crystal, leave XTALO unconnected.

H3

MDIO

I/O

MDIO Data.

H9

AIN14/P4.6

AI/I/O

Analog Input 14 (AIN14).

Digital Input/Output Port 4.6 (P4.6).

H10

AIN12/P4.4

AI/I/O

Analog Input 12 (AIN12).

Digital Input/Output Port 4.4 (P4.4).

H11

AGND4

S

Ground for AVDD4, AVDD_REG0, and AVDD_REG1.

J1

IOVDD3

S

3.3 V GPIO Supply.

J2

XTALI

I

Input to the Crystal Oscillator Inverter and Input to the Internal Clock

Generator Circuits. When not using an external crystal, connect XTALI to

DGND.

J3

VDAC7/P5.2

AO/I/O

Voltage DAC7 Output (VDAC7).

Digital Input/Output Port 5.2 (P5.2).

J4

VDAC4

AO

Voltage DAC4 Output (VDAC4).

J5

AGND1

S

Analog Ground for VDD1.

J6

AIN0

AI

Analog Input 0.

J7

AIN1

AI

Analog Input 1.

J8

AIN2

AI

Analog Input 2.

J9

AIN7

AI

Analog Input 7.

J10

AIN10

AI

Analog Input 10.

J11

AIN11/BUF_VREF2V5

AI/AO

Analog Input 11 (AIN11).

Buffered 2.5 V Bias (BUF_VREF2V5). The maximum load is 1.2 mA. Connect

BUF_VREF2V5 to AGNDx via a 100 nF capacitor.

K1

IOGND3

S

Ground for IOVDD3.

K2

DVDD_2V5

AO

2.5 V Digital Supply. A 470 nF capacitor to IOGND3 must be connected to this

ball to stabilize the internal 2.5 V regulator that supplies the analog digital control.

K3

VDAC6/P5.1

AO/I/O

Voltage DAC6 Output (VDAC6).

Digital Input/Output Port 5.1 (P5.1).

K4

VDAC3/P5.0

AO/I/O

Voltage DAC3 Output (VDAC3).

Digital Input/Output Port 5.0 (P5.0).

K5

VDAC1

AO

Voltage DAC1 Output.

K6

VDD1

S

3.3 V Supply for Digital Die.

K7

AGND2

S

ESD Ground for Pad Ring.

K8

AIN3

AI

Analog Input 3.

K9

AIN6

AI

Analog Input 6. AIN6 is also the positive input for the comparator.

K10

AIN9/P4.3

AI/I/O

Analog Input 9 (AIN9).

Digital Input/Output Port 4.3 (P4.3).