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ADUCM322I Datasheet(PDF) 16 Page - Analog Devices |
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ADUCM322I Datasheet(HTML) 16 Page - Analog Devices |
16 / 23 page ![]() ADuCM322i Data Sheet Rev. 0 | Page 16 of 23 Pin No. Mnemonic Type1 Description B7 RESERVED RES No Connect. Leave this ball unconnected. B8 RESERVED RES No Connect. Leave this ball unconnected. B9 P1.0/SIN/ECLKIN/PLAI[4] I/O Digital Input/Output Port 1.0 (P1.0). UART Input (SIN). External Input Clock (ECLKIN). Input to PLA Element 4 (PLAI[4]). B10 P1.1/SOUT/PLACLK1/PLAI[5] I/O Digital Input/Output Port 1.1 (P1.1). UART Output (SOUT). PLA Clock 1(PLACLK1). Input to PLA Element 5 (PLAI[5]). B11 P1.2/PWM0/PLAI[6] I/O Digital Input/Output Port 1.2 (P1.2). PWM Output 0 (PWM0). Input to PLA Element 6 (PLAI[6]). C1 IOGND1 S Ground for IOVDD1. C2 P0.0/SCLK0/PLAI[0] I/O Digital Input/Output Port 0.0 (P0.0). SPI0 Clock (SCLK0). Input to PLA Element 0 (PLAI[0]). C3 P2.3/BM I/O Digital Input/Output Port 2.3 (P2.3). Boot Mode (BM). This ball determines the start-up sequence after every reset. Pull-up is enabled at power-up. C4 P2.2/IRQ4/POR/CLKOUT/PLAI[10] I/O Digital Input/Output Port 2.2 (P2.2). External Interrupt 4 (IRQ4). Reset Output (POR). This ball function is an output and it is the default for Ball C4. Clock Output (CLKOUT). Input to PLA Element 10 (PLAI[10]). C5 P2.0/IRQ2/PWMTRIP/PLACLK2/PLAI[8] I/O Digital Input/Output Port 2.0 (P2.0). External Interrupt 2 (IRQ2). PWM Trip (PWMTRIP). PLA Input Clock 2 (PLACLK2). Input to PLA Element 8 (PLAI[8]). C6 P1.3/PWM1/PLAI[7] I/O Digital Input/Output Port 1.3 (P1.3). PWM Output 1 (PWM1). Input to PLA Element 7 (PLAI[7]). C7 P1.4/PWM2/SCLK1/PLAO[10] I/O Digital Input/Output Port 1.4 (P1.4). PWM Output 2 (PWM2). SPI1 Clock (SCLK1). Output of PLA Element 10 (PLAO[10]). C8 P1.5/PWM3/MISO1/PLAO[11] I/O Digital Input/Output Port 1.5 (P1.5). PWM Output 3 (PWM3). SPI1 Master In, Slave Out (MISO1). Output of PLA Element 11 (PLAO[11]). C9 P1.6/PWM4/MOSI1/PLAO[12] I/O Digital Input/Output Port 1.6 (P1.6). PWM Output 4 (PWM4). SPI1 Master Out, Slave Input (MOSI1). Output of PLA Element 12 (PLAO[12]). C10 P1.7/IRQ1/PWM5/CS1/PLAO[13] I/O Digital Input/Output Port 1.7 (P1.7). External Interrupt 1 (IRQ1). PWM Output 5 (PWM5). SPI1 Chip Select 1 (CS1). When using SPI1, configure this ball as CS1. Output of PLA Element 13 (PLAO[13]). |
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