Data Sheet

ADuCM322i

Rev. 0 | Page 15 of 23

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 8. Pin Configuration

Table 10. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

A1

RESERVED

RES

No Connect. Leave this ball unconnected.

A2

RESERVED

RES

Connect to AGND.

A3

RESERVED

RES1

Connect to AVDD_REG1.

A4

RESERVED

RES1

Connect to AVDD_REG1.

A5

RESERVED

RES

Connect to AGND.

A6

DGND

S

Power Supply Ground.

A7

RESERVED

RES

Connect to AGND.

A8

RESERVED

RES1

Connect to AVDD_REG1.

A9

RESERVED

RES1

Connect to AVDD_REG1.

A10

RESERVED

RES

Connect to AGND.

A11

IREF

AI

Reference Current. This ball generates the reference current and is set by an

B1

IOVDD1

S

3.3 V GPIO Supply.

B2

RESET

I

Reset Input (Active Low). An internal pull-up resistor is included.

B3

P3.3/PRTADDR3/PLAI[15]

I/O

Digital Input/Output Port 3.3 (P3.3).

MDIO Port Address Bit 3 (PRTADDR3). See the Digital Inputs parameter in

Table 1 for details.

Output of PLA Element 15 (PLAI[15]).

B4

RESERVED

RES

No Connect. Leave this ball unconnected.

B5

RESERVED

RES

No Connect. Leave this ball unconnected.

B6

DGND

S

Power Supply Ground.

1

A

B

C

D

E

F

G

H

J

K

L

2

3

4

5

6

7

8

9

10

11

RESERVED

RESERVED

RESERVED

IOVDD1

IOGND1

P3.3/

PRTADDR3/

PLAI[15]

P0.0/

SCLK0/

PLAI[0]

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

IREF

RESERVED

DGND

DGND2

SWCLK

AIN15/

P4.7

AIN14/

P4.6

AIN12/

P4.4

AIN11/

BUF_

VREF2V5

AIN10

AIN7

AIN2

AIN1

AIN0

AGND1

VDAC4

VDAC7/

P5.2

VDAC6/

P5.1

XTALI

IOVDD3

IOGND3

VDAC3/

P5.0

VDAC1

VDD1

AVDD3

AGND2

AGND3

AIN3

AIN4

AIN6

AIN5

AIN9/

P4.3

AIN8/

P4.2

VDAC0/

P5.3

VDAC2/

P3.7/

PLAO[29]

VDAC5

DGND1

AGND4

AIN13/

P4.5

AVDD4

SWDIO

IOGND2

IOVDD2

DGND

RESERVED

RESERVED

RESERVED

RESERVED

RESET

P1.0/SIN/

ECLKIN/

PLAI[4]

P1.2/

PWM0/

PLAI[6]

P1.1/SOUT/

PLACLK1/

PLAI[5]

P2.4/IRQ5/

ADCCONV/

PWM6/

PLAO[18]

P1.3/

PWM1/

PLAI[7]

P1.4/

PWM2/

SCLK1/

PLAO[10]

P1.5/

PWM3/

MISO1/

PLAO[11]

P1.6/

PWM4/

MOSI1/

PLAO[12]

P1.7/IRQ1/

PWM5/

CS1/

PLAO[13]

P2.0/IRQ2/

PWMTRIP/

PLACLK2/

PLAI[8]

P2.2/

IRQ4/POR/

CLKOUT/

PLAI[10]

P2.3/BM

P0.2/

MOSI0/

PLAI[2]

P0.5/

SDA0/

PLAO[3]

P2.6/

IRQ7/

PLAO[20]

P0.7/

SDA1/

PLAO[5]

P0.6/

SCL1/

PLAO[4]

P3.0/

PRTADDR0/

PLAI[12]

P3.1/

PRTADDR1/

PLAI[13]

P2.7/

IRQ8/

PLAO[21]

P3.5/

MCK/

PLAO[27]

XTALO

MDIO

P0.4/

SCL0/

PLAO[2]

P0.3/

IRQ0/CS0/

PLACLK0/

PLAI[3]

P0.1/

MISO0/

PLAI[1]

P3.2/

PRTADDR2/

PLAI[14]

P3.4/

PRTADDR4/

PLAO[26]

AVDD_

REG0

AVDD_

REG1

VREF_1V2

ADC_

REFP

ADC_

REFN

DVDD_

2V5

DVDD_1V8

ADuCM322i

TOP VIEW

(Not to Scale)

DIGITAL PINS

ANALOG PINS