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ADUCM322I Datasheet(PDF) 10 Page - Analog Devices |
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ADUCM322I Datasheet(HTML) 10 Page - Analog Devices |
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10 / 23 page  ADuCM322i Data Sheet Rev. 0 | Page 10 of 23 Table 5. SPI Master Mode Timing (Phase Mode = 0) Parameter Description Min Typ Max Unit tSL SCLK low pulse width (SPIDIV + 1) × tHCLK/2 ns tSH SCLK high pulse width (SPIDIV + 1) × tHCLK/2 ns tDAV Data output valid after SCLK edge 0 3 ns tDOSU Data output setup before SCLK edge ½ SCLK ns tDSU Data input setup time before SCLK edge SCLK ns tDHD Data input hold time after SCLK edge SCLK ns tDF Data output fall time 25 ns tDR Data output rise time 25 ns tSR SCLK rise time 20 ns tSF SCLK fall time 20 ns Figure 4. SPI Master Mode Timing (Phase Mode = 0) SCLK (POLARITY = 0) SCLK (POLARITY = 1) tSH tSL tSR tSF MOSI MSB BITS 6 TO 1 LSB MISO MSB IN BITS 6 TO 1 LSB IN tDR tDF tDAV tDOSU tDSU tDHD |
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