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ADUCM322I Datasheet(PDF) 9 Page - Analog Devices |
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ADUCM322I Datasheet(HTML) 9 Page - Analog Devices |
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9 / 23 page  Data Sheet ADuCM322i Rev. 0 | Page 9 of 23 SPI Timing Table 4. SPI Master Mode Timing (Phase Mode = 1) Parameter Description Min Typ Max Unit tSL SCLK low pulse width (SPIDIV + 1) × tHCLK/2 ns tSH SCLK high pulse width (SPIDIV + 1) × tHCLK/2 ns tDAV Data output valid after SCLK edge 0 3 ns tDSU Data input setup time before SCLK edge ½ SCLK ns tDHD Data input hold time after SCLK edge SCLK ns tDF Data output fall time SCLK ns tDR Data output rise time 25 ns tSR SCLK rise time 25 ns tSF SCLK fall time 20 ns Figure 3. SPI Master Mode Timing (Phase Mode = 1) SCLK (POLARITY = 0) SCLK (POLARITY = 1) MOSI MSB BITS 6 TO 1 LSB MISO MSB IN BITS 6 TO 1 LSB IN tSH tSL tSR tSF tDR tDF tDAV tDSU tDHD |
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