Micrel, Inc.

PL904xxx

September 11, 2015

3

Revision 1.0

tcghelp@micrel.com or (408) 955-1690

Pin Description

Pin Number

Pin Name

Pin Type

Pin Level

Pin Function

18, 19

22, 23

OUTB, /OUTB

OUTA, /OUTA

O

Various

Clock outputs.

Can be programmed to one of the following logic types:

(1)

LVPECL, LVDS, HCSL, or LVCMOS.

26, 27

REFIN, /REFIN

I

Various

Reference clock input.

Can be programmed to either differential or single-ended use.

20

16

OE_A

OE_B

I

CMOS

Output Enable, Outputs disable to tri-state,

0 = Disabled, 1 = Enabled, on-ch

ip 75kΩ pull-up

1, 2, 5, 8, 25

VDD

PWR

Core power supply.

28

VDDI

PWR

Input circuit power supply, +3.3V only.

24

VDDA

PWR

Analog circuit power supply.

21

17

VDDOA

VDDOB

PWR

Output buffers power supply.

EPAD

VSS

PWR

Power supply ground and thermal relief.

(2)

11

GND

I

This pin is not power supply ground, but must be tied to VSS

for proper operation.

3, 4, 6, 7, 9, 10,

12, 13, 14, 15,

29, 30, 31, 32

DNC

Internally connected. Do not connect anything to these pins.

Note:

1.

In case of LVCMOS, only the true output pin is enabled. The complementary output pin is disabled to a high impedance.

2.

Exposed package pad is electrically active and must be connected to ground.