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STM32F439AI Datasheet(PDF) 133 Page - STMicroelectronics |
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STM32F439AI Datasheet(HTML) 133 Page - STMicroelectronics |
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133 / 240 page ![]() DocID024244 Rev 10 133/240 STM32F437xx and STM32F439xx Electrical characteristics 198 6.3.15 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/ESDA/JEDEC JS-001 and ANSI/ESD S5.3.1 standards. Static latchup Two complementary static tests are required on six parts to assess the latchup performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latchup standard. Table 53. ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum value(1) Unit VESD(HBM) Electrostatic discharge voltage (human body model) TA = +25 °C conforming to ANSI/ESDA/JEDEC JS-001 2 2000 V VESD(CDM) Electrostatic discharge voltage (charge device model) TA = +25 °C conforming to ANSI/ESD S5.3.1, LQFP100/144/176, UFBGA169/176, TFBGA176 and WLCSP143 packages C3 250 TA = +25 °C conforming to ANSI/ESD S5.3.1, LQFP208 package C3 250 1. Guaranteed by characterization results. Table 54. Electrical sensitivities Symbol Parameter Conditions Class LU Static latch-up class TA = +105 °C conforming to JESD78A II level A |
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