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83918 Datasheet(PDF) 6 Page - Integrated Device Technology

Part # 83918
Description  Low Skew, 1:18 Crystal-to-LVCMOS/LVTTL Fanout Buffer
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

83918 Datasheet(HTML) 6 Page - Integrated Device Technology

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©2016 Integrated Device Technology, Inc
Revision B March 17, 2016
83918 Data Sheet
Table 5B. AC Characteristics, VDD = 3.3V±5%,VDDO = 2.5V±5%, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at fOUT unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Refer to the Phase Noise Plot following this section.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
Table 5C. AC Characteristics, VDD = 3.3V±5%,VDDO = 1.8V±0.2V, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at fOUT unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Refer to the Phase Noise Plot following this section.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
200
MHz
tpLH
Propagation Delay, Low to High;
NOTE 1
23
ns
tjit(Ø)
RMS Phase Jitter, (Random);
NOTE 2
25MHz,
Integration Range: 1kHz to 1MHz
0.465
ps
tjit
Additive Phase Jitter, RMS; refer
to Additive Phase Jitter Section
155.52MHz,
Integration Range: 12kHz to 20MHz
0.161
ps
tsk(o)
Output Skew; NOTE 3, 6
75
ps
tsk(pp)
Part-to-Part Skew; NOTE 4, 6
1ns
tR / tF
Output Rise/Fall Time; NOTE 5
20% to 80%
300
700
ps
odc
Output Duty Cycle
ƒOUT  150MHz
45
55
%
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
200
MHz
tpLH
Propagation Delay, Low to High;
NOTE 1
1.65
4.3
ns
tjit(Ø)
RMS Phase Jitter, (Random);
NOTE 2
25MHz,
Integration Range: 1kHz to 1MHz
0.595
ps
tjit
Additive Phase Jitter, RMS; refer
to Additive Phase Jitter Section
155.52MHz,
Integration Range: 12kHz to 20MHz
0.228
ps
tsk(o)
Output Skew; NOTE 3, 6
75
ps
tsk(pp)
Part-to-Part Skew; NOTE 4, 6
1ns
tR / tF
Output Rise/Fall Time; NOTE 5
20% to 80%
200
800
ps
odc
Output Duty Cycle
ƒOUT  150MHz
40
60
%


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