5307 UART Module

1- 2

UART INTERFACE

• TWO INDEPENDENT, FULL DUPLEX ASYNCHRONOUS/SYNCHRONOUS RECEIVER/

• INDEPENDENTLY PROGRAMMABLE BAUD RATE GENERATOR FOR EACH

RECEIVER AND TRANSMITTER DERIVABLE FROM SYSTEM CLOCK

OR EXTERNAL CLOCK ON TIN PIN

• PROGRAMMABLE DATA FORMAT, FIVE TO EIGHT

DATA BITS PLUS PARITY OR ADDRESS MARK BIT

PARITY OPTIONS:

1- ODD PARITY

2- EVEN PARITY

3- FORCE PARITY

4- NO PARITY

• PROGRAMMABLE CHANNEL MODES

NORMAL (FULL DUPLEX)

AUTOMATIC ECHO (HALF DUPLEX)

LOCAL LOOPBACK

REMOTE LOOPBACK

•UART CAN BE PROGRAMMED TO DIRECTLY

INTERRUPT DMA FOR FAST TRANSFERS

TRANSMITTER CHANNELS

OVERVIEW

MCF5307

8K

Unified

Cache

System

Bus

Controller

Interrupt Ctr

2 UARTs

General

Purpose

I/O

M-Bus

JTAG

Debug Rev B

Module

4 DMA

2 Timers

DRAM Cntr

&

Chip Selects

PLL

I Addr Gen

I Fetch1

I Fetch2

I Decode

Instr Buf

Dec&Sel Op

A Gen & Ex

MAC

4K SRAM