5307 UART Module

1- 16

UART INTERRUPT CONTROL

AVEC

-

-

IL2

IL1

IL0

IP1

IP0

AUTOVECTOR

0 - IRQ SOURCE RETURNS VECTOR

1 - SIM GENERATES AVEC FOR IRQ SOURCE

INTERRUPT LEVEL

1 1 1 = IRQ SOURCE HAS HIGHEST PRIORITY

-

-

0 0 1 = IRQ SOURCE HAS LOWEST PRIORITY

0 0 0 = NO INTERRUPT IS REQUESTED

B7.........................................................................................................B0

READ/WRITE

INTERRUPT PRIORITY

1 1 = HIGHEST

-

-

0 0 = LOWEST

IVR7

IVR6

IVR5

IVR4

IVR3

IVR2

IVR1

IVR0

RST:

0

0

0

0

1

1

1

1

READ/WRITE

UIVR - INTERRUPT VECTOR REGISTER