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SPD08N50C3 Datasheet(PDF) 3 Page - Infineon Technologies AG |
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SPD08N50C3 Datasheet(HTML) 3 Page - Infineon Technologies AG |
3 / 11 page ![]() 200 8-04-11 Rev. 2.5 Page 3 SPD08N50C3 Electrical Characteristics , at T j = 25 °C, unless otherwise specified Parameter Symbol Conditions Values Unit min. typ. max. Transconductance gfs VDS≥2*ID*RDS(on)max, ID=4.6A - 6 - S Input capacitance Ciss VGS=0V, VDS=25V, f =1MHz - 750 - pF Output capacitance Coss - 350 - Reverse transfer capacitance Crss - 12 - Effective output capacitance,4) energy related Co(er) VGS=0V, VDS=0V to 400V - 56 - pF Effective output capacitance,5) time related Co(tr) - 30 - Turn-on delay time td(on) VDD=400V, VGS=0/10V, ID=7.6A, RG=12Ω - 6 - ns Rise time tr - 5 - Turn-off delay time td(off) - 60 - Fall time tf - 7 - Gate Charge Characteristics Gate to source charge Qgs VDD=400V, ID=7.6A - 3 - nC Gate to drain charge Qgd - 17 - Gate charge total Qg VDD=400V, ID=7.6A, VGS=0 to 10V - 32 - Gate plateau voltage V(plateau) VDD=400V, ID=7.6A - 5 - V 1Repetitve avalanche causes additional power losses that can be calculated as P AV=EAR*f. 2Device on 40mm*40mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70 µm thick) copper area for drain connection. PCB is vertical without blown air. 3Soldering temperature for TO-263: 220°C, reflow 4C o(er) is a fixed capacitance that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS. 5C o(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. 6I SD<=ID, di/dt<=400A/us, VDClink=400V, Vpeak<VBR, DSS, Tj<Tj,max. Identical low-side and high-side switch. 2013-07-31 2.6 |
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