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CDCLVP111-SP

SCAS946 – NOVEMBER 2016

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Typical Application (continued)

8.2.1.1 Design Requirements

The CDCLVP111-SP shown in Figure 5 is configured to be able to select 2 inputs, a 156.25-MHz LVPECL clock

from the backplane, or a secondary 156.25-MHz LVCMOS 2.5-V oscillator. Either signal can be then fanned out

to desired devices, as shown.

The configuration example is driving 4 LVPECL receivers in a line card application with the following properties:

•

The PHY device has internal AC coupling and appropriate termination and biasing. The CDCLVP111-SP will

need to be provided with 86-Ω emitter resistors near the driver for proper operation.

•

The ASIC is capable of DC coupling with a 2.5-V LVPECL driver such as the CDCLVP111-SP. This ASIC

features internal termination so no additional components are needed.

•

The FPGA requires external AC coupling but has internal termination. Again, 86-Ω emitter resistors are

placed near the CDCLVP111-SP and a 0.1-uF are placed to provide AC coupling. Similarly, the CPU is

internally terminated and requires external AC coupling capacitors.

8.2.1.2 Detailed Design Procedure

Unused outputs can be left floating.

In this example, the PHY, ASIC, and FPGA/CPU require different schemes. Power-supply filtering and bypassing

is critical for low-noise applications.

See Figure 16 for recommended filtering techniques.