LVPECL

Reference

Generator

10

10

QP(9...0)

QN(9...0)

CLKP0

CLKN0

CLKP1

CLKN1

CLK_SEL

+

+

CDCLVP111-SP

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

CDCLVP111-SP

SCAS946 – NOVEMBER 2016

CDCLVP111-SP Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver

1

(1)

Custom temperature ranges available.

1 Features

1

•

Distributes One Differential Clock Input Pair

LVPECL to 10 Differential LVPECL

•

Fully Compatible With LVECL and LVPECL

•

Supports a Wide Supply Voltage Range From

2.375 V to 3.8 V

•

Selectable Clock Input Through CLK_SEL

•

Low-Output Skew (Typical 15 ps) for Clock-

Distribution Applications

–

Additive Jitter Less Than 1 ps

–

Propagation Delay Less Than 355 ps

–

Open Input Default State

–

LVDS, CML, SSTL input Compatible

•

Clocking

•

Frequency Range From DC to 3.5 GHz

•

Supports Defense, Aerospace, and Medical

Applications

–

Controlled Baseline

–

One Assembly and Test Site

–

One Fabrication Site

–

Available in Military (–55°C to 125°C)

–

Extended Product Life Cycle

–

Extended Product-Change Notification

–

Product Traceability

2 Applications

•

Designed for Driving 50-Ω Transmission Lines

•

High-Performance Clock Distribution

3 Description

The CDCLVP111-SP clock driver distributes one

differential clock pair of LVPECL input, (CLK0, CLK1)

to ten pairs of differential LVPECL clock (Q0, Q9)

outputs with minimum skew for clock distribution. The

CDCLVP111-SP can accept two clock sources into

an

input

multiplexer.

The

CDCLVP111-SP

is

specifically designed for driving 50-

Ω transmission

lines. When an output pin is not used, leaving it open

is recommended to reduce power consumption. If

only one of the output pins from a differential pair is

used, the other output pin must be identically

terminated to 50

Ω.

ended input operation is required. In this case, the

to GND via a 10-nF capacitor.

For high-speed performance, the differential mode is

strongly recommended.

The CDCLVP111-SP is characterized for operation

from –55°C to 125°C.

Device Information(1)

PART NUMBER

PACKAGE

BODY SIZE (NOM)

CDCLVP111-SP

HFG (36)

9.08 mm × 9.08 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Functional Block Diagram