CDCLVP111-EP datasheet(19/23 Pages) TI1

Part #	CDCLVP111-EP

Description	Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver

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Manufacturer	TI1 [Texas Instruments]

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Place decoupling caps near device

Any input clock termination

required can be placed fly-by on

bottom of board beneath device

50

to (VCC ± 2 Plane)

differential routing

CDCLVP111-SP

19

CDCLVP111-SP

www.ti.com

SCAS946 – NOVEMBER 2016

Product Folder Links: CDCLVP111-SP

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10 Layout

10.1 Layout Guidelines

Differential outputs should be length matched and impedance controlled with 50 Ω to (VCC – 2) or 100-Ω

differential with proper endpoint LVPECL termination. Clock inputs should be biased near device pins.

10.2 Layout Example

Figure 17. CDCLVP111-SP Layout Example

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