CDCLVP111-EP datasheet(17/23 Pages) TI1

Part #	CDCLVP111-EP

Description	Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver

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CDCLVP111-SP

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SCAS946 – NOVEMBER 2016

Product Folder Links: CDCLVP111-SP

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Typical Application (continued)

8.2.1.3 Application Curves

The CDCLVP111-SP low-additive noise can be shown in this line card application. The low-noise, 110.22-MHz

signal with 47-fs RMS jitter drives the CDCLVP111-SP, resulting in 192-fs RMS when integrated from 10 kHz to

20 MHz. The resultant-additive jitter is a low 186-fs RMS for this configuration.

Reference signal is low noise signal generator

Figure 14. CDCLVP111-SP Reference Phase Noise

47-fs RMS

(10 kHz to 20 MHz)

Figure 15. CDCLVP111-SP Output Phase Noise

192-fs RMS

(10 kHz to 20 MHz)

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