CLK_SEL

VBB

30

31

29

28

27

26

23

22

24

21

20

19

18

17

15

14

13

12

11

10

5

CLK0

CLK0

CLK1

CLK1

0

1

3

4

6

7

2

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Q0

Q1

Q2

Q3

Q4

Q5

Q7

Q6

Q9

Q8

+

+

-

-

-

-

-

9

CDCLVP111-SP

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SCAS946 – NOVEMBER 2016

Product Folder Links: CDCLVP111-SP

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Copyright © 2016, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The CDCLVP111-SP is an open emitter for LVPECL outputs. Therefore, proper biasing and termination are

required to ensure correct operation of the device and to minimize signal integrity. The proper termination for

LVPECL outputs is 50

equivalent circuit is worked out for the LVPECL termination in both direct-coupled (DC) and AC-coupled

receiver end. If the supply voltage for the driver and receiver is different, AC coupling is required.

7.2 Functional Block Diagram

7.3 Feature Description

The CDCLVP111-SP is a low-additive jitter universal to LVPECL fan out buffer with 2 selectable inputs. The

small package, low-output skew, and low-additive jitter make for a flexible device in demanding applications.