NB7VPQ701M

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3

DEVICE CONFIGURATION

Pin

Description

Logic State

Equalization Gain

EQ

Equalization Amount

Low

3 dB

Mid

6 dB

High

9 dB

Pin

Description

Logic State

De−emphasis Ratio (Note 1)

OS = LOW

OS = Float

OS = High

DE

De−Emphasis Amount

Low

0 dB

−4 dB

−6 dB

Mid

−3 dB

−5.5 dB

−7.5 dB

High

−5.5 dB

−7 dB

−9 dB

Pin

Description

Logic State

Output Swing

OS

Output Swing with DE Pin Low

(0 dB)

Low

Mid

High

Pin

Description

Logic State

Chip Enable

EN

Chip Enable Input

Low

Chip Disabled (Deep Power−Saving Mode)

High

Chip Enable

Table 3. ATTRIBUTES

Parameter

ESD Protection

Human Body Model

Charged Device Model

> 4 kV

> 1.5 kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2)

Level 1

Flammability Rating

Oxygen Index: 28 to 34

UL 94 V−O @ 0.125 in

Transistor Count

704

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

2. For additional information, see Application Note AND8003/D.

Table 4. ABSOLUTE MAXIMUM RATINGS

Over operating free−air temperature range (unless otherwise noted)

Parameter

Description

Min

Max

Unit

Supply Voltage (Note 3)

−0.3

2.5

V

Voltage range at any input or

output terminal

Differential I/O

−0.5

1.89

V

LVCMOS inputs

−0.3

V

Electrostatic discharge

Human body model (all pins) (Note 4)

±4

kV

Charged device model (all pins) (Note 4)

±1.5

kV

−65

150

°C

−40

125

°C

Junction−to−ambient thermal resistance,

138

°C/W

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

3. All voltage values are with respect to the GND terminals.

4. Tested in accordance with JEDEC Standard.