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BD81A24MUV-M Datasheet(PDF) 2 Page - Rohm

Part # BD81A24MUV-M
Description  4ch White LED Driver with Buck-Boost
Download  40 Pages
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Manufacturer  ROHM [Rohm]
Direct Link  http://www.rohm.com
Logo ROHM - Rohm

BD81A24MUV-M Datasheet(HTML) 2 Page - Rohm

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BD81A24MUV-M/EFV-M
TSZ02201-0T3T0C600070-1-2
© 2016 ROHM Co., Ltd. All rights reserved.
2016.10.19 Rev.003
www.rohm.com
TSZ22111・15・001
Pin Description
Pin Configuration
VQFN28SV5050 (Top view)
HTSSOP-B28 (Top view)
Block Diagram
OSC
Control Logic
Current driver
Open Short Detect
VREG
VREG
VCC
EN
UVLO
TSD
PWM
Timer
Latch
VDISC
OVP10
OVP
OCP
OVP
CS
FAIL1
RT
SYNC
SLOPE
PWM
BOOT
OUTH
SW
DRV
CTL
OUTL
DGND
VREG
ERRAMP
LED1
LED2
LED3
LED4
COMP
SS
OCP OVP
SS
PGND
ISET
PWM
Open Det
Short Det
Timer
Latch
FAIL2
ISET
GND
SHDETEN
LEDEN1 LEDEN2
VQFN28
SV5050
HTSSOP
-B28
Terminal
Name
Function
1
11
LEDEN1
LED output pin enable terminal 1
2
12
LEDEN2
LED output pin enable terminal 2
3
13
LED1
LED output terminal 1
4
14
LED2
LED output terminal 2
5
15
LED3
LED output terminal 3
6
16
LED4
LED output terminal 4
7
17
OVP
Over-voltage detection terminal
8
18
ISET
LED output current setting terminal
9
19
PGND
LED output GND terminal
10
20
OUTL
Low side FET drain terminal
11
21
DGND
DC/DC output GND terminal
12
22
VDISC
Output voltage discharge terminal
13
23
SW
High side FET source terminal
14
24
OUTH
High side FET gate terminal
15
25
BOOT
High side FET driver power supply terminal
16
26
VREG
Internal constant voltage
17
27
EN
Enable terminal
18
28
CS
DC/DC current sense terminal
19
1
VCC
Input power supply terminal
20
2
SS
“Soft Start” Capacitor connection
21
3
COMP
ERR AMP output
22
4
RT
Oscillation Frequency-setting resistor input
23
5
SYNC
External synchronization input terminal
24
6
SHDETEN
Short detection enable signal
25
7
GND
Small signal GND terminal
26
8
PWM
PWM light modulation input terminal
27
9
FAIL1
“Failure” signal output terminal
28
10
FAIL2
LED open/short detection output signal
-
-
Thermal
PAD
Back side thermal PAD
(Please connect to GND)
Figure 2. Pin Configuration
Figure 3. Internal Block Diagram


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