TM124BBK32, TM124BBK32S 1048576 BY 32-BIT

TM248CBK32, TM248CBK32S 2097152 BY 32-BIT

DYNAMIC RAM MODULE

SMMS132D – JANUARY 1991 – REVISED JUNE 1995

9

POST OFFICE BOX 1443

timing requirements over recommended range of supply voltage and operating free-air

temperature (concluded)

’124BBK32-60

’248CBK32-60

’124BBK32-70

’248CBK32-70

’124BBK32-80

’248CBK32-80

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

tCAL

Delay time, column address to CAS high

30

35

40

ns

tRPC

Delay time, RAS high to CAS low (CBR refresh only)

0

0

0

ns

tRSH

Delay time, CAS low to RAS high

15

18

20

ns

tTAA

Access time from address (test mode)

35

40

45

ns

tTRAC

Access time from RAS (test mode)

65

75

85

ns

tTCPA

Access time from column precharge (test mode)

40

45

50

ns

tREF

Refresh time interval

16

16

16

ms

tT

Transition time

2

50

2

50

2

50

ns

device symbolization (TM124BBK32 illustrated)

TM124BBK36B

–SS

YYMMT

YY = Year Code

MM = Month Code

T = Assembly Site Code

–SS = Speed Code

NOTE: Location of symbolization may vary.