TM124BBK32, TM124BBK32S 1048576 BY 32-BIT

TM248CBK32, TM248CBK32S 2097152 BY 32-BIT

DYNAMIC RAM MODULE

SMMS132D – JANUARY 1991 – REVISED JUNE 1995

8

POST OFFICE BOX 1443

timing requirements over recommended range of supply voltage and operating free-air

temperature

’124BBK32-60

’248CBK32-60

’124BBK32-70

’248CBK32-70

’124BBK32-80

’248CBK32-80

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

tRC

Cycle time, random read or write (see Note 7)

110

130

150

ns

tPC

Cycle time, page-mode read or write (see Note 8)

40

45

50

ns

tCP

Pulse duration, CAS high

10

10

10

ns

tCAS

Pulse duration, CAS low

15

10 000

18

10 000

20

10 000

ns

tRP

Pulse duration, RAS high (precharge)

40

50

60

ns

tRASP

Pulse duration, page mode, RAS low

60

100 000

70

100 000

80

100 000

ns

tRAS

Pulse duration, nonpage mode, RAS low

60

10 000

70

10 000

80

10 000

ns

tWP

Pulse duration, write

15

15

15

ns

tASC

Setup time, column address before CAS low

0

0

0

ns

tASR

Setup time, row address before RAS low

0

0

0

ns

tDS

Setup time, data

0

0

0

ns

tRCS

Setup time, read before CAS low

0

0

0

ns

tWCS

Setup time, W low before CAS low

0

0

0

ns

tWSR

Setup time, W high (CBR refresh only)

10

10

10

ns

tCWL

Setup time, W low before CAS high

15

18

20

ns

tRWL

Setup time, W low before RAS high

15

18

20

ns

tWTS

Setup time, W low (test mode only)

10

10

10

ns

tCAH

Hold time, column address after CAS low

10

15

15

ns

tRAH

Hold time, row address after RAS low

10

10

10

ns

tAR

Hold time, column address after RAS low (see Note 9)

50

55

60

ns

tDHR

Hold time, data after RAS low (see Note 9)

50

55

60

ns

tDH

Hold time, data

10

15

15

ns

tRCH

Hold time, read after CAS high (see Note 10)

0

0

0

ns

tRRH

Hold time, read after RAS high (see Note 10)

0

0

0

ns

tWCH

Hold time, write after CAS low

15

15

15

ns

tWHR

Hold time, W high (CBR refresh only)

10

10

10

ns

tWCR

Hold time, write after RAS low

50

55

60

ns

tWTH

Hold time, W low (test mode only)

10

10

10

ns

tCSH

Delay time, RAS low to CAS high

60

70

80

ns

tCRP

Delay time, CAS high to RAS low

0

0

0

ns

tRCD

Delay time, RAS low to CAS low (see Note 11)

20

45

20

52

20

60

ns

tCHR

Delay time, RAS low to CAS high (CBR refresh only)

15

15

20

ns

tCSR

Delay time, CAS low to RAS low (CBR refresh only)

10

10

10

ns

tRAD

Delay time, RAS low to column address (see Note 11)

15

30

15

35

15

40

ns

tRAL

Delay time, column address to RAS high

30

35

40

ns

NOTES:

7. All cycle times assume tT = 5 ns.

8. To assure tPLmin, tASC should be ≥ 5 ns.

9. The minimum value is measured when tRCD is set to tRCD min as a reference.

10. Either tRRH or tRCH must be satisfied for a read cycle.

11. Maximum value specified only to assure access time.