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MCP16251 Datasheet(PDF) 9 Page - Microchip Technology

Part # MCP16251
Description  Low Quiescent Current, PFM/PWM Synchronous Boost Regulator with True Output Disconnect or Input/Output Bypass Option
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP16251 Datasheet(HTML) 9 Page - Microchip Technology

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 2013 - 2016 Microchip Technology Inc.
DS20005173B-page 9
MCP16251/2
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
3.1
Feedback Voltage Pin (VFB)
The VFB pin is used to provide output voltage regulation
by using a resistor divider. Feedback voltage will
typically be 1.23V, with the output voltage in regulation.
3.2
Signal Ground Pin (SGND)
The signal ground pin is used as a return for the
integrated VREF and error amplifier. In the 2x3x0.8
TDFN package, the SGND and power ground (PGND)
pins are connected externally.
3.3
Power Ground Pin (PGND)
The power ground pin is used as a return for the
high-current N-Channel switch. In the 2x3x0.8 TDFN
package, the PGND and signal ground (SGND) pins are
connected externally.
3.4
Enable Pin (EN)
The EN pin is a logic-level input used to enable or
disable device switching and lower quiescent current
while disabled. A logic high (>70% of VIN) will enable
the regulator output. A logic low (<20% of VIN) will
ensure that the regulator is disabled.
3.5
Switch Node Pin (SW)
Connect the inductor from the input voltage to the SW
pin. The SW pin carries inductor current and can be as
high
as
650 mA
typical
peak.
The
integrated
N-Channel switch drain and integrated P-Channel
switch source are internally connected at the SW node.
3.6
Output Voltage Power Pin (VOUTP)
The output voltage power pin connects the output volt-
age to the switch node. High current flows through the
integrated P-Channel and out of this pin to the output
capacitor and output. In the 2x3x0.8 TDFN package,
VOUTS and VOUTP are connected externally.
3.7
Output Voltage Sense Pin (VOUTS)
The output voltage sense pin connects the regulated
output voltage to the internal bias circuits. In the
2x3x0.8 TDFN package, VOUTS and VOUTP are
connected externally.
3.8
PowerSupply InputVoltage Pin (VIN)
Connect the input voltage source to VIN. The input
source should be decoupled to GND with a 4.7 µF
minimum capacitor.
3.9
Exposed Thermal Pad (EP)
There is no internal electrical connection between the
Exposed Thermal Pad (EP) and the PGND and SGND
pins. They must be connected to the same potential on
the Printed Circuit Board (PCB).
3.10
Ground Pin (GND)
The ground or return pin is used for circuit ground
connection. Length of trace from input cap return,
output cap return and GND pin should be made as
short as possible to minimize noise on the GND pin. In
the SOT23-6 package, a single ground pin is used.
3.11
Output Voltage Pin (VOUT)
The output voltage pin connects the integrated
P-Channel MOSFET to the output capacitor. The
feedback voltage divider is also connected to the VOUT
pin for voltage regulation.
TABLE 3-1:
PIN FUNCTION TABLE
MCP16251/2
SOT-23
MCP16251/2
TDFN 2x3x0.8
Symbol
Description
4
1
VFB
Feedback Voltage Pin
2
SGND
Signal Ground Pin
3
PGND
Power Ground Pin
3
4
EN
Enable Control Input Pin
1
5
SW
Switch Node, Boost Inductor Input Pin
6
VOUTP
Output Voltage Power Pin
7
VOUTS
Output Voltage Sense Pin
6
8
VIN
Input Voltage Pin
9
EP
Exposed Thermal Pad (EP); must be connected to SGND and PGND.
2
GND
Ground Pin
5
VOUT
Output Voltage Pin


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