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ML7202-001 Datasheet(PDF) 4 Page - LAPIS Semiconductor Co., Ltd. |
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ML7202-001 Datasheet(HTML) 4 Page - LAPIS Semiconductor Co., Ltd. |
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4 / 65 page  FEDL7202-001-01 ML7202-001 4/65 PIN DESCRIPTIONS Pin Symbol I/O State when PDN/RST =”0” Description 1 DGND1 — — Digital ground pin 2 D0 I/O I 3 D1 I/O I 4 D2 I/O I 5 D3 I/O I 6 D4 I/O I 7 D5 I/O I 8 D6 I/O I 9 D7 I/O I Data I/O pins for accessing control registers. This LSI contains 32-byte control registers and reads/writes by an external microcontroller are via the WR, RD, and CS pins. See “Microcontroller Interface Write/Read Timing” in the “ELECTRICAL CHARACTERISTICS” Section. 10 WR I I Write enable input pin for accessing the control registers 11 RD I I Read enable input pin for accessing the control registers. This pin is enabled when the MTYPE pin is set to “0” and is disabled when the MTYPE pin is set to “1”. When this pin is disabled, fix this pin to “1”. 12 CS I I Chip select input pin for the control registers 13 PDN/RST I “0” Power-down and reset control input pin. When this pin is set to ”0”, the LSI is powered down. In power down mode, all of the control registers, internal data memories, coefficients in the echo canceler and the ADPCM transcoder are reset. For normal operation, set this pin to “1”. Since the power-down reset function is determined by the OR’ed value of a negative logic of this pin and the CR0-B7 (SPDN), set the CR0-B7 (SPDN) to “0” when using the pin. When applying power, hold the pin in “0” for 250 S or longer from the master clock input (20 clocks minimum) after the digital supply (DVDD1 and DVDD2) voltage and the analog supply (AVDD) voltage reach 90% of their nominal value. See “Reset Function” in the “TIMING DIAGRAM” Section. Note that the specifications prescribed in this data sheet may not be satisfied until the requirements of inputting a minimum of 20 master clock pulses and holding the pin in “0” for 250 S or more are met. 14 TSTI7 I I Input pin for LSI manufacturer’s tests. Fix this pin to “0”. 15 MCK I I Master clock input pin. The input frequency shall be 19.2 MHz. The master clock can be asynchronized to SYNCL, SYNCA, BCLKL, and BCLKA. 16 AGND — — Analog ground pin 17 SG O “0” Output pin for analog signal ground in the LSI. The output voltage is about 1.4 V. Connect 10 F and 0.1 F (ceramic type) bypass capacitors between this pin and the AGND pin. This output cannot be directly used as analog signal ground. A buffer should be placed when this output is used. 18 AVDD — — +3.3 V analog power supply pin |
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