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ML7202-001 Datasheet(PDF) 7 Page - LAPIS Semiconductor Co., Ltd. |
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ML7202-001 Datasheet(HTML) 7 Page - LAPIS Semiconductor Co., Ltd. |
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7 / 65 page  FEDL7202-001-01 ML7202-001 7/65 Pin Symbol I/O PDN/RST =”0” Description 30 IS2 O Hi-Z ADPCM data output pin on the transmit side of channel 2. When CR0-B3 (IOSEL) is set to “1”, the signal that is input from the PCMADI2 pin is output from this pin. When CR0-B3 is set to “0”, the signal that is input from the PCMLNII2 pin is output. ADPCM data is output serially starting from MSB, synchronized to the rising edges of BCLKA and SYNCA, and this pin gets in a high impedance state except when the 4-bit ADPCM data is being output. Also during power-down/reset and initial mode, this pin is put in a high impedance state. When CR3-B7 (CONTA2) is set to “1”, this pin is configured as an 8-bit PCM data output skipping the ADPCM transcoder. This pin gets in a high impedance state except when the 8-bit PCM data is being output. When CR3-B5 (DTHR2) is set to “1”, the 4-bit ADPCM input data from the input pin set by CR0-B3 (IOSEL) is output from this pin as it is. This pin gets in a high impedance state except when the 4-bit ADPCM data is being output. When CR3-B5 (DTHR2) is set to “1”, the MUTE function is disabled, and the pin is not configured as an 8-bit PCM data output even if CR3-B7 (CONTA2) is set to “1”. 31 DVDD2 — — +3.3 V digital power supply pin 32 VOUT2 O About 2.6 V Regulator output pin. The output voltage is about 2.6 V. Connect 10 F and 0.1 F bypass capacitors between this pin and the DGND2 pin. 33 DGND2 — — Digital Ground pin 34 PCMADO1 O Hi-Z PCM data output pin of channel 1. This pin is enabled when CR0-B3 (IOSEL) is set to “1” and is put in a high impedance state when CR0-B3 is set to “0”. The PCM data is output serially starting from MSB, synchronized to the rising edges of BCLKL and SYNCL, and the pin gets in a high impedance state except when the 8-bit PCM data is being output. Also during power-down reset and initial mode, the pin is also put in a high impedance. When CR2-B5 (DTHR1) is set to “1”, this pin is configured as a 4-bit ADPCM data output and 4-bit ADPCM input data from the IR1 pin is output as it is. This pin gets in a high impedance state except when the 4-bit ADPCM data is being output. When CR2-B7 (CONTA1) is set to “1”, the ADPCM transcoder goes into a through mode and 8-bit PCM input data from the IR1 pin is output as it is from this pin. The pin gets in a high impedance state except when the 8-bit PCM data is being output. When CR2-B5 (DTHR1) is set to “1”, the MUTE function is disabled and the pin is not configured as an 8-bit PCM data output even if CR2-B7 (CONTA1) is set to “1”. |
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Similar Description - ML7202-001 |
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