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CLC1005 Datasheet(PDF) 14 Page - Exar Corporation |
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CLC1005 Datasheet(HTML) 14 Page - Exar Corporation |
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14 / 19 page  © 2007-2015 Exar Corporation 14 / 19 exar.com/CLC1005 Rev 2D CLC1005, CLC1015, CLC2005 0 0.5 1 1.5 -40 -20 0 20 40 60 80 Ambient Temperature (°C) MSOP-8 SOIC-8 TSOT-5 TSOT-6 Figure 7. Maximum Power Derating Driving Capacitive Loads Increased phase delay at the output due to capacitive loading can cause ringing, peaking in the frequency response, and possible unstable behavior. Use a series resistance, RS, between the amplifier and the load to help improve stability and settling performance. Refer to Figure 8. + - Rf Input Output Rg Rs CL RL Figure 8. Addition of RS for Driving Capacitive Loads Table 1 provides the recommended RS for various capacitive loads. The recommended RS values result in approximately <1dB peaking in the frequency response. CL (pF) RS (Ω) -3dB BW (MHz) 22pF 0 118 47pF 15 112 100pF 15 91 492pF 6.5 59 Table 1: Recommended RS vs. CL For a given load capacitance, adjust RS to optimize the tradeoff between settling time and bandwidth. In general, reducing RS will increase bandwidth at the expense of additional overshoot and ringing. Layout Considerations General layout and supply bypassing play major roles in high frequency performance. Exar has evaluation boards to use as a guide for high frequency layout and as an aid in device testing and characterization. Follow the steps below as a basis for high frequency layout: ■ ■ Include 6.8µF and 0.1µF ceramic capacitors for power supply decoupling ■ ■ Place the 6.8µF capacitor within 0.75 inches of the power pin ■ ■ Place the 0.1µF capacitor within 0.1 inches of the power pin ■ ■ Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance ■ ■ Minimize all trace lengths to reduce series inductances Refer to the evaluation board layouts below for more information. Evaluation Board Information The following evaluation boards are available to aid in the testing and layout of these devices: Evaluation Board # Products CEB002 CLC1005 and CLC1015 in TSOT CEB003 CLC1005 in SOIC CEB006 CLC2005 in SOIC CEB010 CLC2005 in MSOP Evaluation Board Schematics Evaluation board schematics and layouts are shown in Figures 9-18. These evaluation boards are built for dual- supply operation. Follow these steps to use the board in a single-supply application: 1. Short -VS to ground. 2. Use C3 and C4, if the -VS pin of the amplifier is not directly connected to the ground plane. |
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