Data Sheet

4

Rev. 1.0, 2011-04-08

IFX1050GVIO

Pin Configuration

2

Pin Configuration

Figure 1

Pin Configuration IFX1050GVIO (top view)

Table 1

Pin Definitions and Functions IFX1050GVIO

Pin No. Symbol

Function

1TxD

CAN transmit data input; 20 k

Ω pull-up, LOW in dominant state

2GND

Ground

3

V

CC

5 V Supply input

4RxD

CAN receive data output; LOW in dominant state,

integrated pull-up

5

V

33V

Logic supply input; 3.3V or 5V microcontroller logic supply can be connected here! The

digital I/Os of the IFX1050GVIO adopt to the connected microcontroller logic supply a

V

33V

6CANL

Low line I/O; LOW in dominant state

7CANH

High line I/O; HIGH in dominant state

8INH

Inhibit Input; control input, 20 k

Ω pull, set LOW for normal mode

1

TxD

2

GND

3

4

RxD

8

7

6

5

CANH

CANL

INH

IFX1050GVIO

(PG-DSO-8)