ASAHI KASEI

[AK5384]

MS0225-E-00

2003/05

- 17 -

SYSTEM DESIGN

Figure 10 shows the system connection diagram. An evaluation board is available which demonstrates application circuits,

the optimum layout, power supply arrangements and measurement results.

0.1

µ

10

µ

LIN2+

1

2

3

4

5

6

7

8

9

10

11

LIN2-

RIN2+

RIN2-

TEST

VCOM

AVSS

AVDD

DIF

TDM1

TDM0

AK5384

DSP and uP

28

27

26

LIN1+

LIN1-

RIN1+

Analog Supply

4.75 ~ 5.25V

12 TDMIN

13 MCLK

14 OVF

Reset

25

24

RIN1-

M/S

23

22

CKS

PDN

DVSS

DVDD

19

18

TVDD

SDTO1

17

16

SDTO2

BICK

15

LRCK

0.1

µ

10

µ

Digital Supply

4.75 ~ 5.25V

20

21

0.1

µ

Digital Supply

3.0 ~ 5.25V

0.1

µ

2.2

µ

Note:

- AVSS and DVSS of the AK5384 should be distributed separately from the ground of external digital devices

(MPU, DSP etc.).

- All digital input pins should not be left floating.

Figure 10. Typical Connection Diagram (Normal mode)