ASAHI KASEI

[AK5384]

MS0225-E-00

2003/05

- 12 -

OPERATION OVERVIEW

n System Clock

The external clocks which are required to operate the AK5384 are MCLK(256fs/384fs/512fs/768fs), BICK(48fs

∼),

LRCK(1fs) in slave mode (M/S pin = “L”). MCLK should be synchronized with LRCK but the phase is not critical. When

384fs, 512fs or 768fs clock is input to MCLK pin, the internal master clock becomes 256fs(=384fs x 2/3=512fs x

1/2=768fs x 1/3) automatically. Table 1 illustrates standard audio word rates and corresponding frequencies used in the

AK5384.

In master mode (M/S pin = “H”), MCLK select 256fs or 512fs by CKS pin. But 384fs and 768fs are not supported. 512fs

does not support 96kHz sampling.

All external clocks (MCLK, BICK, LRCK) should always be present whenever the AK5384 is in normal operation mode

(PDN pin = “H”). If these clocks are not provided, the AK5384 may draw excess current and may fall into unpredictable

operation. This is because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the

AK5384 should be in the power-down mode (PDN pin = “L”). After exiting reset at power-up etc., the AK5384 is in the

power-down mode until MCLK and LRCK are input. In master mode, the master clock (MCLK) must be provided unless

PDN pin = “L”.

MCLK

BICK

fs

256fs

384fs

512fs

768fs

64fs

128fs

32.0kHz

8.1920MHz

12.2880MHz

16.3840MHz

24.576MHz

2.0480MHz

4.0960MHz

44.1kHz

11.2896MHz

16.9344MHz

22.5792MHz

33.8688MHz

2.8224MHz

5.6448MHz

48.0kHz

12.2880MHz

18.4320MHz

24.5760MHz

36.8640MHz

3.0720MHz

6.1440MHz

96.0kHz

24.5760MHz

36.8640MHz

N/A

N/A

6.1440MHz

N/A

Table 1. System clock example (Slave mode)

MCLK

CKS

8kHz

≤ fs ≤ 48kHz

48kHz

< fs ≤ 96kHz

L

256fs

256fs

H

512fs

N/A

Table 2. Master clock frequency select (Master mode)

n Audio Interface Format

12 types of audio data interface can be selected by the TDM1-0, M/S and DIF pins as shown in Table 3. The audio data

format can be selected by the DIF pin. In all formats the serial data is MSB-first, 2's compliment format. The SDTO1/2 is

clocked out on the falling edge of BICK.

In normal mode, Mode 0-1 are the slave mode, and BICK is available up to 128fs at fs=48kHz. BICK outputs 64fs clock in

Mode 2-3.

In TDM256 mode, the serial data of all ADC (four channels) is output from the SDTO1/2 pins. BICK should be fixed to

256fs. In the slave mode, “H” time and “L” time of LRCK should be 1/256fs at least. In the master mode, “H” time (“L”

time at I

In TDM128 mode, the serial data of all ADC (four channels) is output from the SDTO1 pin. The SDTO2 output is fixed to

“L”. BICK should be fixed to 128fs. In the slave mode, “H” time and “L” time of LRCK should be 1/128fs at least. In the

master mode, “H” time (“L” time at I