ASAHI KASEI

[AK5384]

MS0225-E-00

2003/05

- 8 -

Parameter

Symbol

min

typ

max

Units

Audio Interface Timing (Slave mode)

Normal mode (TDM1=“L”, TDM0=“L”)

BICK Period

BICK Pulse Width Low

Pulse Width High

LRCK Edge to BICK “

↑”

(Note 11)

BICK “

↑” to LRCK Edge

(Note 11)

LRCK to SDTO1/2 (MSB) (Except I

BICK “

↓” to SDTO1/2

tBCK

tBCKL

tBCKH

tLRB

tBLR

tLRS

tBSD

160

65

65

30

30

35

35

ns

ns

ns

ns

ns

ns

ns

TDM256 mode (TDM1=“L”, TDM0=“H”)

BICK Period

BICK Pulse Width Low

Pulse Width High

LRCK Edge to BICK “

↑”

(Note 11)

BICK “

↑” to LRCK Edge

(Note 11)

BICK “

↓” to SDTO1/2

tBCK

tBCKL

tBCKH

tLRB

tBLR

tBSD

81

32

32

20

20

20

ns

ns

ns

ns

ns

ns

TDM128 mode (TDM1=“H”, TDM0=“H”)

BICK Period

BICK Pulse Width Low

Pulse Width High

LRCK Edge to BICK “

↑”

(Note 11)

BICK “

↑” to LRCK Edge

(Note 11)

BICK “

↓” to SDTO1

(Note 12)

tBCK

tBCKL

tBCKH

tLRB

tBLR

tBSD

81

32

32

20

20

20

ns

ns

ns

ns

ns

ns

Audio Interface Timing (Master mode)

Normal mode (TDM1=“L”, TDM0=“L”)

BICK Frequency

BICK Duty

BICK “

↓” to LRCK

BICK “

↓” to SDTO1/2

fBCK

dBCK

tMBLR

tBSD

−20

−40

64fs

50

20

40

Hz

%

ns

ns

TDM256 mode (TDM1=“L”, TDM0=“H”)

BICK Frequency

BICK Duty

(Note 13)

BICK “

↓” to LRCK

BICK “

↓” to SDTO1/2

fBCK

dBCK

tMBLR

tBSD

−12

−20

256fs

50

12

20

Hz

%

ns

ns

TDM128 mode (TDM1=“H”, TDM0=“H”)

BICK Frequency

BICK Duty

BICK “

↓” to LRCK

BICK “

↓” to SDTO1

(Note 12)

fBCK

dBCK

tMBLR

tBSD

−12

−20

128fs

50

12

20

Hz

%

ns

ns

Power-Down & Reset Timing

PDN Pulse Width

(Note 14)

PDN “

↑” to SDTO1/2 valid

(Note 15)

tPD

tPDV

150

516

ns

1/fs

Note 11. BICK rising edge must not occur at the same time as LRCK edge.

Note 12. SDTO2 output is fixed to “L”.

Note 13. This value is MCLK=512fs. Duty cycle is not guaranteed when MCLK=256fs/384fs.

Note 14. The AK5384 can be reset by bringing the PDN pin = “L”.

Note 15. This cycle is the number of LRCK rising edges from the PDN pin = “H”.