AD5546/AD5556

Rev. 0 | Page 12 of 16

DIGITAL SECTION

The AD5546/AD5556 have 16-/14-bit parallel inputs. The

devices are double-buffered with 16-/14-bit registers. The

double-buffered feature allows the update of several AD5546/

AD5556 simultaneously. For AD5546, the input register is

loaded directly from a 16-bit controller bus when the WR pin is

brought low. The DAC register is updated with data from the

input register when LDAC is brought high. Updating the DAC

register updates the DAC output with the new data (see

Figure 19). To make both registers transparent, tie WR low and

LDAC high. The asynchronous RS pin resets the part to zero

scale if MSB pin = 0, and midscale if MSB pin = 1.

ESD PROTECTION CIRCUITS

All logic input pins contain back-biased ESD protection Zeners

a result, the voltage level of the logic input should not be greater

than the supply voltage.

5k

Ω

DIGITAL

INPUTS

DGND

Figure 20. Equivalent ESD Protection Circuits

AMPLIFIER SELECTION

In addition to offset voltage, the bias current is important in op

amp selection for precision current output DACs. An input bias

current of 30 nA in the op amp contributes to 1 LSB in the

AD5546’s full-scale error. Op amps OP1177 and AD8628 are

good candidates for the I-V conversion.

REFERENCE SELECTION

The initial accuracy and the rated output of the voltage refer-

ence determine the full span adjustment. The initial accuracy is

usually a secondary concern in precision, as it can be trimmed.

Figure 25 shows an example of a trimming circuit. The zero

scale error can also be minimized by standard op amp nulling

techniques.

The voltage reference temperature coefficient and long-term

drift are primary considerations. For example, a 5 V reference

per degree Celsius. As a result, the reference that operates at

Similarly, the same 5 V reference with a ±50 ppm long-term

drift means that the output may change by ±250 µV over time.

Therefore, it is practical to calibrate a system periodically to

maintain its optimum precision.