AD5546/AD5556

Rev. 0 | Page 7 of 16

Pin No.

Mnemonic

Description

15

LDAC

Digital Input Load DAC Control. Signal level must be

16

WR

Write Control Digital Input in Active Low. Transfers shift-register data to DAC register on rising edge. Signal level

must be

17

MSB

Power On Reset State. MSB = 0 resets at zero-scale, MSB = 1 resets at midscale. Signal level must be

18

RS

Reset in Active Low. Resets to zero-scale if MSB = 0 and resets to midscale if MSB = 1. Signal level must be

19

GND

Analog and Digital Grounds.

20–27

D13 to D6

Digital Input Data Bits D13 to D6. Signal level must be

28

Positive power supply input. Specified range of operation: 2.7 V to 5.5 V.

WR

DATA

LDAC

RS

Figure 5. AD5546/AD5556 Timing Diagram

Table 5. AD5546 Parallel Input Data Format

MSB

LSB

Bit Position

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Data Word

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Table 6. AD5556 Parallel Input Data Format

MSB

LSB

Bit Position

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Data Word

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Table 7. Control Inputs

RS

WR

LDAC

Register Operation

0

X

X

Reset output to 0, with MSB pin = 0. Midscale with MSB pin = 1.

1

0

0

Load input register with data bits.

1

1

1

Load DAC register with the contents of the input register.

1

0

1

Input and DAC registers are transparent.

1

When LDAC and WR are tied together and programmed as a pulse, the data bits are loaded into the input register on

the falling edge of the pulse, and then loaded into the DAC register on the rising edge of the pulse.

1

1

0

No register operation.