SWCS044-001

ADCL

MMICP

MMICN

HMICP

HMICN

ADCR

SMICP

SMICN

AFMR

AFML

HSL

HSR

HFLP

HFLN

HFRP

HFRN

EARP

EARN

AUXLP

AUXLN

AUXRP

AUXRN

VIBLP

VIBLN

PDM

to

PCM

PCM

to

PWM

VIBRP

VIBRN

PDM

interface

I

2

C

registers

HS LDO

LS LDO

Negative

charge

pump

GNDHFR

VDDHFR

GNDHFL

VDDHFL

GNDHS

VSSHS

VDDHS

VDDEAR

VSSEAR

GNDVIBL

VDDVIBL

PDMCLK

PDMCLKLB

PDMFRAME

PDMDN

PDMUP

HP PLL

LP PLL

VSSLDO

VDDLDO

MCLK

CLK32K

Reference

temp

sense

REF

GNDREF

SDA

SCL

Accessory

connector

detection

HMBIAS

DMBIAS1

MBIAS

DMBIAS2

MMBIAS

DBIAS1

DBIAS2

UL0

UL1

DL0

DL1

DL2

DL3

DL4

0:30 dB

VDDREGNCP

CFLYP

NCPOUT

–52:6 dB

–52:6 dB

–30:0 dB

–24:6 dB

–30:0 dB

–18:24 dB

AAFL

AAFR

MicAmpL

MicAmpR

LineInAmpR

LineInAmpL

EarDrv

HSLDrv

HSRDrv

HFLDrv

HFRDrv

VIBLDrv

VIBRDrv

PGAL

PGAR

HFDACL

HFDACR

HSDACR

HSDACL

HBIAS

Osc

Uplink

Downlink

Clock system

Power

Interface

CFLYN

GNDNCP

VSSPLL

VDDPLL

VDDUL

VSSUL

GNDVCM

VDDAMBIAS

VDDDMBIAS

VDDDL

VSSDL

LB0

LB1

GNDAMIC

GNDDMIC

VSSLDOIN

ACCONN

GNDVIBR

VDDVIBR

GNDLDO

VDDV2V1

PBKG

GPO1(2,3)

VDDVIO

PCM

to

PWM

NCPFB

1

1

1

1

1

1

1

1

1

8

8

8

8

8

8

1

1

PLUGDET

0:30 dB

REFP

REFN

TWL6040

www.ti.com

SWCS052B – AUGUST 2010 – REVISED AUGUST 2014

1.4

Functional Block Diagram

Figure 1-1 shows the system block diagram of the TWL6040 device.

Figure 1-1. Simplified Block Diagram

Copyright © 2010–2014, Texas Instruments Incorporated

Device Overview

3

Submit Documentation Feedback

Product Folder Links: TWL6040