SC16C2550 datasheet(27/46 Pages) PHILIPS

Part #	SC16C2550

Description	Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder

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Manufacturer	PHILIPS [NXP Semiconductors]

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27 / 46 page

Philips Semiconductors

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

Product data

Rev. 03 — 19 June 2003

27 of 46

9397 750 11621

[1]

Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated.

7.9 Scratchpad Register (SPR)

The SC16C2550 provides a temporary data register to store 8 bits of user

information.

7.10 Enhanced Feature Register (EFR)

Enhanced features are enabled or disabled using this register.

Bits 0 through 4 provide single or dual character software ﬂow control selection.

When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double

8-bit words are concatenated into two sequential numbers.

1

MSR[1]

∆DSR [1]

Logic 0 = No DSR change (normal default condition).

Logic1=The DSR input to the SC16C2550 has changed state

since the last time it was read. A modem Status Interrupt will be

generated.

0

MSR[0]

∆CTS [1]

Logic 0 = No CTS change (normal default condition).

Logic 1 = The CTS input to the SC16C2550 has changed state

since the last time it was read. A modem Status Interrupt will be

generated.

Table 19:

Modem Status Register bits description…continued

Bit

Symbol

Description

Table 20:

Enhanced Feature Register bits description

Bit

Symbol

Description

7

EFR[7]

Automatic CTS ﬂow control.

Logic0=Automatic CTS ﬂow control is disabled (normal default

condition).

Logic 1 = Enable Automatic CTS ﬂow control. Transmission will stop

when CTS goes to a logical 1. Transmission will resume when the CTS

pin returns to a logical 0.

6

EFR[6]

Automatic RTS ﬂow control. Automatic RTS may be used for hardware ﬂow

control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will

be generated when the receive FIFO is ﬁlled to the programmed trigger

level and RTS will go to a logic 1 at the next trigger level. RTS will return to

a logic 0 when data is unloaded below the next lower trigger level

(programmed trigger level 1). The state of this register bit changes with the

status of the hardware ﬂow control. RTS functions normally when

hardware ﬂow control is disabled.

0 = Automatic RTS ﬂow control is disabled (normal default condition).

1 = Enable Automatic RTS ﬂow control.

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