SC16C2550 datasheet(26/46 Pages) PHILIPS

Part #	SC16C2550

Description	Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder

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Manufacturer	PHILIPS [NXP Semiconductors]

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26 / 46 page

Philips Semiconductors

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

Product data

Rev. 03 — 19 June 2003

26 of 46

9397 750 11621

7.8 Modem Status Register (MSR)

This register provides the current state of the control interface signals from the

modem, or other peripheral device to which the SC16C2550 is connected. Four bits

of this register are used to indicate the changed information. These bits are set to a

logic 1 whenever a control input from the modem changes state. These bits are set to

a logic 0 whenever the CPU reads this register.

1

LSR[1]

Overrun error.

Logic 0 = No overrun error (normal default condition).

Logic1=Overrun error. A data overrun error occurred in the

receive shift register. This happens when additional data arrives

while the FIFO is full. In this case, the previous data in the shift

register is overwritten. Note that under this condition, the data

byte in the receive shift register is not transferred into the FIFO,

therefore the data in the FIFO is not corrupted by the error.

0

LSR[0]

Receive data ready.

Logic 0 = No data in receive holding register or FIFO (normal

default condition).

Logic 1 = Data has been received and is saved in the receive

holding register or FIFO.

Table 18:

Line Status Register bits description…continued

Bit

Symbol

Description

Table 19:

Modem Status Register bits description

Bit

Symbol

Description

7

MSR[7]

CD. During normal operation, this bit is the complement of the CD

input. Reading this bit in the loop-back mode produces the state of

MCR[3] (OP2).

6

MSR[6]

RI. During normal operation, this bit is the complement of the RI

input. Reading this bit in the loop-back mode produces the state of

MCR[2] (OP1).

5

MSR[5]

DSR. During normal operation, this bit is the complement of the

DSR input. During the loop-back mode, this bit is equivalent to

MCR[0] (DTR).

4

MSR[4]

CTS. During normal operation, this bit is the complement of the

CTS input. During the loop-back mode, this bit is equivalent to

MCR[1] (RTS).

3

MSR[3]

∆CD [1]

Logic 0 = No CD change (normal default condition).

Logic 1 = The CD input to the SC16C2550 has changed state

since the last time it was read. A modem Status Interrupt will be

generated.

2

MSR[2]

∆RI [1]

Logic 0 = No RI change (normal default condition).

Logic 1 = The RI input to the SC16C2550 has changed from a

logic 0 to a logic 1. A modem Status Interrupt will be generated.

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