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SC16C2550 Datasheet(PDF) 22 Page - NXP Semiconductors |
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SC16C2550 Datasheet(HTML) 22 Page - NXP Semiconductors |
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22 / 46 page  Philips Semiconductors SC16C2550 Dual UART with 16 bytes of transmit and receive FIFOs and IrDA encoder/decoder Product data Rev. 03 — 19 June 2003 22 of 46 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Table 12: Interrupt Status Register bits description Bit Symbol Description 7-6 ISR[7-6] FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not being used in the 16C450 mode. They are set to a logic 1 when the FIFOs are enabled in the SC16C2550 mode. Logic 0 or cleared = default condition. 5-4 ISR[5-4] INT priority bits 4-3. These bits are enabled when EFR[4] is set to a logic 1. ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5] indicates that CTS, RTS have been generated. Note that once set to a logic 1, the ISR[4] bit will stay a logic 1 until Xon character(s) are received. Logic 0 or cleared = default condition. 3-1 ISR[3-1] INT priority bits 2-0. These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (see Table 11). Logic 0 or cleared = default condition. 0 ISR[0] INT status. Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine. Logic 1 = No interrupt pending (normal default condition). Table 13: Line Control Register bits description Bit Symbol Description 7 LCR[7] Divisor latch enable. The internal baud rate counter latch and Enhance Feature mode enable. Logic 0 = Divisor latch disabled (normal default condition). Logic 1 = Divisor latch enabled. 6 LCR[6] Set break. When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a logic 0 state). This condition exists until disabled by setting LCR[6] to a logic 0. Logic 0 = no TX break condition (normal default condition) Logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the remote receiver to a line break condition. 5-3 LCR[5-3] Programs the parity conditions (see Table 14). 2 LCR[2] Stop bits. The length of stop bit is specified by this bit in conjunction with the programmed word length (see Table 15). Logic 0 or cleared = default condition. 1-0 LCR[1-0] Word length bits 1, 0. These two bits specify the word length to be transmitted or received (see Table 16). Logic 0 or cleared = default condition. |
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