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SC16C2550 Datasheet(PDF) 20 Page - NXP Semiconductors |
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SC16C2550 Datasheet(HTML) 20 Page - NXP Semiconductors |
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20 / 46 page  Philips Semiconductors SC16C2550 Dual UART with 16 bytes of transmit and receive FIFOs and IrDA encoder/decoder Product data Rev. 03 — 19 June 2003 20 of 46 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 7.3.2 FIFO mode Table 9: FIFO Control Register bits description Bit Symbol Description 7-6 FCR[7] (MSB), FCR[6] (LSB) RCVR trigger. These bits are used to set the trigger level for the receive FIFO interrupt. Logic 0 (or cleared) = normal default condition. Logic 1 = RX trigger level. An interrupt is generated when the number of characters in the FIFO equals the programmed trigger level. However, the FIFO will continue to be loaded until it is full. Refer to Table 10. 5-4 FCR[5-4] Not used; initialized to logic 0. 3 FCR[3] DMA mode select. Logic 0 = Set DMA mode ‘0’ Logic 1 = Set DMA mode ‘1’ Transmit operation in mode ‘0’: When the SC16C2550 is in the 16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no characters in the transmit FIFO or transmit holding register, the TXRDY pin in PLCC44 or LQFP48 packages will be a logic 0. Once active, the TXRDY pin will go to a logic 1 after the first character is loaded into the transmit holding register. Receive operation in mode ‘0’: When the SC16C2550 is in mode ‘0’ (FCR[0] = logic 0), or in the FIFO mode (FCR[3] = logic 0) and there is at lease one character in the receive FIFO, the RXRDY pin will be a logic 0. Once active, the RXRDY pin on PLCC44 and LQFP48 packages will go to a logic 1 when there are no more characters in the receiver. Transmit operation in mode ‘1’: When the SC16C2550 is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin on PLCC44 and LQFP48 packages will be a logic 1 when the transmit FIFO is completely full. It will be a logic 0 if one or more FIFO locations are empty. Receive operation in mode ‘1’: When the SC16C2550 is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached, or a Receive Time-Out has occurred, the RXRDY pin on PLCC44 and LQFP48 packages will go to a logic 0. Once activated, it will go to a logic 1 after there are no more characters in the FIFO. 2 FCR[2] XMIT FIFO reset. Logic 0 = Transmit FIFO not reset (normal default condition). Logic 1 = Clears the contents of the transmit FIFO and resets the FIFO counter logic (the transmit shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. |
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