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SC16C2550 Datasheet(PDF) 15 Page - NXP Semiconductors |
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SC16C2550 Datasheet(HTML) 15 Page - NXP Semiconductors |
15 / 46 page ![]() Philips Semiconductors SC16C2550 Dual UART with 16 bytes of transmit and receive FIFOs and IrDA encoder/decoder Product data Rev. 03 — 19 June 2003 15 of 46 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. data that is then made available at the user data interface D0-D7. The user optionally compares the received data to the initial transmitted data for verifying error-free operation of the UART TX/RX circuits. In this mode, the receiver and transmitter interrupts are fully operational. The Modem Control Interrupts are also operational. Fig 6. Internal loop-back mode diagram. TRANSMIT FIFO REGISTER TXA, TXB RECEIVE SHIFT REGISTER RECEIVE FIFO REGISTER RXA, RXB SC16C2550 TRANSMIT SHIFT REGISTER MODEM CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR XTAL2 XTAL1 DATA BUS AND CONTROL LOGIC D0–D7 IOR IOW RESET A0–A2 CSA, CSB REGISTER SELECT LOGIC INTA, INTB TXRDYA, TXRDYB RXRDYA, RXRDYB INTERRUPT CONTROL LOGIC 002aaa120 MCR[4] = 1 CTSA, CTSB RTSA, RTSB DSRA, DSRB DTRA, DTRB RIA, RIB (OP1A, OP1B) CDA, CDB (OP2A, OP2B) |
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