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SC16C2550 Datasheet(PDF) 13 Page - NXP Semiconductors |
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SC16C2550 Datasheet(HTML) 13 Page - NXP Semiconductors |
13 / 46 page ![]() Philips Semiconductors SC16C2550 Dual UART with 16 bytes of transmit and receive FIFOs and IrDA encoder/decoder Product data Rev. 03 — 19 June 2003 13 of 46 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. receive holding register (RHR) is read. The actual time-out value is 4 character time, including data information length, start bit, parity bit, and the size of stop bit, i.e., 1 ×, 1.5 ×, or 2× bit times. 6.8 Programmable baud rate generator The SC16C2550 supports high speed modem technologies that have increased input data rates by employing data compression schemes. For example, a 33.6 kbit/s modem that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s. The SC16C2550 can support a standard data rate of 921.6 kbit/s. A single baud rate generator is provided for the transmitter and receiver, allowing independent TX/RX channel control. The programmable Baud Rate Generator is capable of operating with a frequency of up to 80 MHz. To obtain maximum data rate, it is necessary to use full rail swing on the clock input. The SC16C2550 can be configured for internal or external clock operation. For internal clock oscillator operation, an industry standard microprocessor crystal is connected externally between the XTAL1 and XTAL2 pins. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates (see Table 6). The generator divides the input 16 × clock by any divisor from 1 to 216 − 1. The SC16C2550 divides the basic external clock by 16. The basic 16 × clock provides table rates to support standard and custom applications using the same system design. The rate table is configured via the DLL and DLM internal register functions. Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate generator. Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB) provides a user capability for selecting the desired final baud rate. The example in Table 6 shows the selectable baud rate table available when using a 1.8432 MHz external clock input. Fig 5. Crystal oscillator connection. 002aaa169 X1 1.8432 MHz C1 22 pF C2 47 pF X1 1.8432 MHz C1 47 pF C2 100 pF 1.5 k Ω |
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