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SC16C2550 Datasheet(PDF) 1 Page - NXP Semiconductors |
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SC16C2550 Datasheet(HTML) 1 Page - NXP Semiconductors |
1 / 46 page ![]() SC16C2550 Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder Rev. 03 — 19 June 2003 Product data 1. Description The SC16C2550 is a 2 channel Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbits/s. The SC16C2550 is pin compatible with the ST16C2550. It will power-up to be functionally equivalent to the 16C2450. The SC16C2550 provides enhanced UART functions with 16-byte FIFOs, modem control interface, DMA mode data transfer. The DMA mode data transfer is controlled by the FIFO trigger levels and the TXRDY and RXRDY signals. On-board status registers provide the user with error indications and operational status. System interrupts and modem control features may be tailored by software to meet specific user requirements. An internal loop-back capability allows on-board diagnostics. Independent programmable baud rate generators are provided to select transmit and receive baud rates. The SC16C2550 operates at 5 V, 3.3 V and 2.5 V and the Industrial temperature range, and is available in plastic PLCC44, LQFP48 and DIP40 packages. 2. Features s 2 channel UART s 5 V, 3.3 V and 2.5 V operation s Industrial temperature range s Pin and functionally compatible to 16C2450 and software compatible with INS8250, SC16C550 s Up to 5 Mbits/s data rate at 5 V and 3.3 V, and 3 Mbits/s at 2.5 V s 16 byte transmit FIFO to reduce the bandwidth requirement of the external CPU s 16 byte receive FIFO with error flags to reduce the bandwidth requirement of the external CPU s Independent transmit and receive UART control s Four selectable Receive FIFO interrupt trigger levels s Automatic software/hardware flow control s Programmable Xon/Xoff characters s Software selectable Baud Rate Generator s Sleep mode s Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break) s Transmit, Receive, Line Status, and Data Set interrupts independently controlled |
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