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SC16C2550 Datasheet(PDF) 9 Page - NXP Semiconductors |
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SC16C2550 Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 46 page ![]() Philips Semiconductors SC16C2550 Dual UART with 16 bytes of transmit and receive FIFOs and IrDA encoder/decoder Product data Rev. 03 — 19 June 2003 9 of 46 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 6. Functional description The SC16C2550 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character (character orientated protocol). Data integrity is insured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to provide all these functions is fairly complex, especially when manufactured on a single integrated silicon chip. The SC16C2550 represents such an integration with greatly enhanced features. The SC16C2550 is fabricated with an advanced CMOS process. The SC16C2550 is an upward solution that provides a dual UART capability with 16 bytes of transmit and receive FIFO memory, instead of none in the 16C2450. The SC16C2550 is designed to work with high speed modems and shared network environments that require fast data processing time. Increased performance is realized in the SC16C2550 by the transmit and receive FIFOs. This allows the external processor to handle more networking tasks within a given time. For example, the ST16C2450 without a receive FIFO, will require unloading of the RHR in 93 microseconds (this example uses a character length of 11 bits, including start/stop bits at 115.2 kbits/s). This means the external CPU will have to service the receive FIFO less than every 100 microseconds. However, with the 16 byte FIFO in the SC16C2550, the data buffer will not require unloading/loading for 1.53 ms. This increases the service interval, giving the external CPU additional time for other applications and reducing the overall UART interrupt servicing time. In addition, the four selectable receive FIFO trigger interrupt levels is uniquely provided for maximum data throughput performance especially when operating in a multi-channel environment. The FIFO memory greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. The SC16C2550 is capable of operation up to 5 Mbits/s with a 80 MHz clock. With a crystal or external clock input of 7.3728 MHz, the user can select data rates up to 460.8 kbits/s. The rich feature set of the SC16C2550 is available through internal registers. Selectable receive FIFO trigger levels, selectable TX and RX baud rates, and modem interface controls are all standard features. Following a power-on reset or an external reset, the SC16C2550 is software compatible with the previous generation, ST16C2450. 6.1 UART A-B functions The UART provides the user with the capability to bi-directionally transfer information between an external CPU, the SC16C2550 package, and an external serial device. A logic 0 on chip select pins CSA and/or CSB allows the user to configure, send data, and/or receive data via UART channels A-B. Individual channel select functions are shown in Table 3. |
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