DS1085

19 of 21

9) This indicates the time taken between power-up and the outputs becoming active. An on-chip delay is

clock cycles and hence depends on the programmed clock frequency.

10) Output voltage swings can be impaired at high frequencies combined with high-output loading.

11) After this period, the first clock pulse is generated.

12) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the

SCL signal.

then be met. This is automatically the case if the device does not stretch the LOW period of the SCL

signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data

released.

16) EEPROM write begins after a STOP condition occurs.

17) Typical frequency shift due to aging is ±0.5%. Aging stressing includes Level 1 moisture reflow

preconditioning (24hr +125

°C bake, 168hr 85°C/85%RH moisture soak, and 3 solder reflow passes

+240 +0/-5

55

°C to +125°C, 96hr 130°C/85%RH/5.5V HAST and 168hr 121°C/2 ATM Steam/Unbiased

Autoclave.

Figure 5. MASTER FREQUENCY TEMPERATURE VARIATION

M A S T E R F R E Q U E NCY T E M P E R AT URE

V ARIAT IO N

-2 .0 0

-1 .5 0

-1 .0 0

-0 .5 0

0.00

0.50

1.00

1.50

2.00

66 .00

82.75

99 .5 0

116.25

133.00

M A S TE R O S CILL A TO R F R E Q UE NCY (M Hz )