STK541UC60C-E

www.onsemi.com

6

Test Circuit

The tested phase U+ shows the upper side of the U phase and U

 shows the lower side of the U phase.

■ ICE / IR(BD)

U+

V+

W+

U-

V-

W-

M

11

11

11

9

6

3

N

9

6

3

13

13

13

U(BD)

V(BD)

W(BD)

M

8

5

2

N

23

23

23

Fig.1

■ VCE(SAT) (test by pulse)

U+

V+

W+

U-

V-

W-

M

11

11

11

9

6

3

N

9

6

3

13

13

13

m

14

15

16

17

18

19

Fig.2

■ VF (test by pulse)

U+

V+

W+

U-

V-

W-

M

11

11

11

9

6

3

N

9

6

3

13

13

13

Fig.3

■ ID

VD1

VD2

VD3

VD4

M

8

5

2

22

N

9

6

3

23

Fig.4

ICE

8

M

A

VD1=15V

9

5

VD2=15V

6

VCE

2

VD3=15V

3

22

VD4=15V

23

N

8

M

VD1=15V

9

5

VD2=15V

6

V

Ic

2

VD3=15V

VCE(SAT)

3

22

VD4=15V

m

N

23

M

V

VF

IF

N

ID

A

M

VD*

N